1. Field of the Invention
The present invention relates in general to a circuit for controlling a data output buffer of a semiconductor memory device, and more particularly to a data output buffer control circuit for controlling an operating point of the data output buffer according to the presence of a repaired memory cell in the semiconductor memory device to enhance a data read speed of the semiconductor memory device.
2. Description of the Prior Art
Generally, a data output buffer control circuit is adapted to generate an output enable signal synchronously with a time point that a data signal read from memory cells is arrived at an input line of a data output buffer. However, the read data signal when a repaired memory cell is present among the memory cells is arrived at the input line of the data output buffer later than that when no repaired memory cell is present among the memory cells. Namely, a semiconductor memory device including the repaired memory cell has a data read speed lower than that including no repaired memory cell. The lower data read speed based on the presence of the repaired memory cell causes the data output buffer to generate error data in response to the earlier output enable signal from the data output buffer control circuit.
In order to overcome the above problem, there has been proposed a data output buffer control circuit which comprises a delay circuit including an inverter chain and a capacitor for delaying an address transition detect signal from an address transition detector. In the case where the semiconductor memory device has the repaired memory cell, such a conventional data output buffer control circuit with the delay circuit generates an output enable signal synchronously with the read data signal from the memory cells of the semiconductor memory device being supplied to the input line of the data output buffer, to allow the data output buffer to buffer accurately the data signal. However, in the case where the semiconductor memory device has no repaired memory cell, the conventional data output buffer control circuit generates the output enable signal delayed by a delay time of the delay circuit from the read data signal from the memory cells of the semiconductor memory device being supplied to the input line of the data output buffer, resulting in a degradation in a response speed of the data output buffer for the input. As a result, the conventional data output buffer control circuit has the disadvantage that it degrades the data read speed of the semiconductor memory device including no repaired memory cell.